Nexperia 74AHC132D-Q100J, Quad 2-Input NANDSchmitt Trigger Logic Gate, 14-Pin SOIC

Quad 2-input NAND Schmitt trigger, The 74AHC132-Q100, 74AHCT132-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC132-Q100, 74AHCT132-Q100 contains four 2‑input NAND gates which accept standard input signals. They can transform slowly changing input signals into sharply defined, jitter free output signals. The gate switches at different points for positive‑going and negative‑going signals. The difference between the positive voltage VT+ and the negative VT‑ is defined as the hysteresis voltage VH.

Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Balanced propagation delays
Inputs accept voltages higher than VCC